Regułowy model logiczny rekonfigurowalnego sterownika logicznego do weryfikacji i syntezy

The article presents rule-based logical model of reconfigurable logic controller, by means of Control Interpreted Petri Nets, which are formal specification of discrete systems behavior. Regulowy model logiczny rekonfigurowalnego sterownika logicznego... 75 Logical model, as an abstract description, is easy to formally verify and to synthesize. It corresponds to the functionality of Moore automaton (Fig. 1) with input (optionally) and output registers. Logical model, derived from Control Interpreted Petri Net (Fig. 2) contains variables with initial values, rules describing system behavior (transition firings) and changes of input and output signals. In the paper, various rules notations are discussed – model oriented on transitions (Fig. 3), transitions and places, places (Fig. 4) and finally model oriented on preconditions and postconditions. Model checking technique is used as formal verification method. Logical model is transformed into NuSMV (model checker) input format according to some strictly defined rules. It is possible to simulate prepared model description. After delivery of requirements list, which are supposed to be satisfied, model checker tool can formally verify system description. Logical model can be also transformed into synthesizable code in VHDL, according to some strictly defined rules. For places representation one-hot encoding was used, which is recommended for implementation in FPGAs. VHDL model can be firstly simulated, i.e. in Active HDL environment. It can be also synthesized in form of rapid prototyping, i.e. in XILINX PlanAhead environment. As a support for testing, an application was developed, which allows automatic conversion of rule-based specification of reconfigurable logic controller into model description for formal verification and into synthesizable code. Researches were based on Xilinx FPGA’s. The result of applying proposed methods is the assurance that verified behavioral specification in temporal logic will be an abstract program of matrix reconfigurable logic controller. So, logic controller program (its implementation) will be valid according to its primary specification. This may shorten the duration time of RLCs development process and, consequently, save money.