Impact of polysilicon emitter interfacial layer engineering on the 1/f noise of bipolar transistors

To optimize the electrical characteristics of polysilicon emitter bipolar transistors, the poly emitter interface needs careful engineering. In this paper, bipolar transistors of a 0.5 /spl mu/m BiCMOS process have been fabricated with intentionally grown oxides in an LPCVD cluster for precise control over the interfacial oxide thickness and uniformity. The trade off between current gain enhancement and increased 1/f noise will be discussed for various interfacial oxide thicknesses and emitter annealing conditions. It will be demonstrated that for sufficiently large base currents, both for large (20 /spl mu/m/spl times/20 /spl mu/m) and small (0.5 /spl mu/m/spl times/5 /spl mu/m) emitter areas the interfacial oxide dominates the 1/f noise spectrum of the base current. Hence, the polysilicon emitter interface engineering will not only set the current gain at a predefined value, but at the same time the associated oxide-tunnelling noise is fixed, within the constraint that the emitter-base junction depth is constant. Finally, it will be shown that the current gain enhancement and increased 1/f noise have compensating effects on the output noise of practical circuits.

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