Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic Networks

We demonstrate a new approach to minimizing the total of the static and th,e dgnamic power dissipation com.ponen#ts in a CMOS logic network required to operate at, a specified clock frequency using joint optimizatioii of both device and circuit designs for a specific logic schematic and activity profile. We present a new approach to designing ultra low-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths for a specified speed constraint. The static (leakage) and dynamic (switching) energy components are considered and an efficient heuristic is develop~cl that delivers over an order of magnitude savings in power over conventional optimization methods.