A novel gain error background calibration algorithm for time-interleaved ADCs

This paper presents a background calibration technique for gain error in Time-interleaved (TI) analog-to-digital converters (ADCs). The presented calibration technique is based on statistical characteristics of the input signal and error information can be obtained by analyzing the statistical properties of the input signal. Compared with conventional calibration algorithm, the presented calibration in this paper has low hardware resource consumption and no restriction on the input signal frequency, and can be extended to arbitrary number of channels. Simulation of the 8-bit 5-channel TIADCs with MATLAB shows that with gain error in the range of ±5% Vref, SNR of the output signal of the TIADCs is only 29.8dBc and reach 47.9dBc after calibration. The TIADCs performance is enhanced significantly by using this calibration algorithm.

[1]  Shing-Chow Chan,et al.  A Novel Iterative Structure for Online Calibration of $M$-channel Time-Interleaved ADCs , 2014, IEEE Transactions on Instrumentation and Measurement.

[2]  Emiliano Sisinni,et al.  New Architecture for a Wireless Smart Sensor Based on a Software-Defined Radio , 2011, IEEE Transactions on Instrumentation and Measurement.

[3]  Christian Vogel,et al.  The impact of combined channel mismatch effects in time-interleaved ADCs , 2005, IEEE Transactions on Instrumentation and Measurement.

[4]  Bo Yan,et al.  Estimation and calibration for channel mismatches in high-speed ADC systems , 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

[5]  Shing-Chow Chan,et al.  Design and Complexity Optimization of a New Digital IF for Software Radio Receivers With Prescribed Output Accuracy , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Jun Shan Wang,et al.  Adaptive Calibration of Channel Mismatches in Time-Interleaved ADCs Based on Equivalent Signal Recombination , 2014, IEEE Transactions on Instrumentation and Measurement.

[7]  Mario Rafael Hueda,et al.  A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques , 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

[8]  Qi Yu,et al.  A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Zhang Qing-hong Time-domain Measurement and Calibration of Mismatch Errors in Multi-chip ADC Time-interleaved Systems , 2005 .

[10]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.