Analysis of various body bias under near-threshold-voltage CMOS circuits

In this paper, we analyzed near-threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

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