High voltage SOI CMOS IC technology for driving plasma display panels

We have developed a new high voltage CMOS (HV-CMOS) IC technology by using 5 /spl mu/m-thick SOI. In this technology, trench isolation and a 0.5 /spl mu/m rule CMOS process are also adopted. We have examined seven series HV-CMOS fabrication processes in different voltage ratings (in which the maximum voltage rating was 250 V) and optimized their characteristics respectively. The HV-CMOS IC with full-CMOS type level shifter is suited to low power consumption color plasma display panels (C-PDPs) and high-speed switching has been confirmed. The chip size of the developed PDP scan driver IC could be reduced by 40% compared with the conventional chip.

[1]  M. Nakano,et al.  Full-complementary high-voltage driver ICs for flat display panels , 1989, International Symposium on VLSI Technology, Systems and Applications,.

[2]  I. Omura,et al.  Prospects of high voltage power ICs on thin SOI , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[3]  K. Kobayashi,et al.  A 5 to 130 V level shifter composed of thin gate oxide dual terminal drain PMOSFETS , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.