Synthesis of Data Path Architecture with Online Fault Detection Mechanism for Reconfigurable Systems

The emergence of reconfigurable computing has opened up the possibility of a new research field in the area of digital design. The processing element is the main computational unit of a Reconfigurable Cell. With the advent in VLSI technology, several Processing Elements can be used to obtain complex functions and a major challenge is to guarantee their fault free operation. In this paper, we present the design and implementation of a reconfigurable data path with online fault detection mechanism. The data path performs addition and multiplication operations and a fault detection mechanism based on the control signals as well as nature of operands respectively. A fault detection mechanism is introduced to detect the faults while the data path is in operation. The design was modeled using Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. The design was also synthesized in Leonardo Spectrum. A comparison was made by implementing the design in different FPGA devices. The results show that the proposed data path has better device utilization and less delay in Virtex 5 FPGA and a fault detection mechanism is implemented with less area and delay overhead.