Investigation of ESD performance in advanced CMOS technology

........................................................................................................... v Acknowledgments .............................................................................................. vii List of Tables .................................................................................................... xiii List of Figures ..................................................................................................... xv

[1]  J.J. Liou,et al.  Electrostatic discharge in semiconductor devices: protection techniques , 2000, Proceedings of the IEEE.

[2]  K. Ng,et al.  The impact of intrinsic series resistance on MOSFET scaling , 1986, IEEE Transactions on Electron Devices.

[3]  Sung-Mo Kang,et al.  Modeling of Electrical Overstress in Integrated Circuits , 1994 .

[4]  S.M.Sze,et al.  Surface States and Barrier Height of Metal‐Semiconductor Systems , 1965 .

[5]  Gaudenzio Meneghesso,et al.  ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[6]  S. Beebe,et al.  Characterization, modeling, and design of ESD protection circuits , 1998 .

[7]  A. Heringa,et al.  The effect of silicide on ESD performance , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[8]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[9]  K. Varahramyan,et al.  A model for specific contact resistance applicable for titanium silicide-silicon contacts , 1996 .

[10]  A. Yu,et al.  Electron tunneling and contact resistance of metal-silicon contact barriers , 1970 .

[11]  H. Grubin The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[12]  C. R. Crowell Richardson constant and tunneling effective mass for thermionic and thermionic-field emission in Schottky barrier diodes , 1969 .

[13]  K. Ng,et al.  On the calculation of specific contact resistivity on , 1990 .

[14]  W. Joyce,et al.  Analytic approximations for the Fermi energy of an ideal Fermi gas , 1977 .

[15]  R.W. Dutton,et al.  Bipolar transistor modeling of avalanche generation for computer circuit simulation , 1975, IEEE Transactions on Electron Devices.

[16]  A. Amerasekera,et al.  Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .

[17]  A. Amerasekera,et al.  ESD failure modes: characteristics mechanisms, and process influences , 1992 .

[18]  F. Segal,et al.  A CHARACTERIZATION OF FIBRANT SEGAL CATEGORIES , 2006, math/0603400.

[19]  G. Reimbold,et al.  Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[20]  Gianluca Boselli,et al.  On High Injection Mechanisms in Semiconductor Devices under ESD Conditions , 2001 .

[21]  Kai Esmark Device simulation of ESD protection elements , 2001 .

[22]  Kueing-Long Chen The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors , 1988 .

[23]  C. Duvvury,et al.  Design Methodology For Optimizing Gate Driven ESD Protection Circuits In Submicron Cmos Processes , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[24]  Kaustav Banerjee,et al.  Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[25]  Liang-sheng Lu,et al.  [Expression of fusion proteins in beta(2)GP I gene-transfected HEp-2 cells and its clinical application]. , 2002, Zhonghua yi xue za zhi.

[26]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[27]  G. Notermans On the use of n-well resistors for uniform triggering of ESD protection elements , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[28]  N. Arora MOSFET Models for VLSI Circuit Simulation , 1993 .

[29]  S. Ramaswamy,et al.  Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations , 1996, Proceedings of International Reliability Physics Symposium.

[30]  C. Duvvury,et al.  Substrate pump NMOS for ESD protection applications , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[31]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[32]  W. Fichtner,et al.  TCAD software for ESD on-chip protection design , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[33]  C. R. Crowell,et al.  Normalized thermionic-field (T-F) emission in metal-semiconductor (Schottky) barriers , 1969 .

[34]  X. Guggenmos,et al.  Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[35]  R. N. Rountree ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[36]  Charvaka Duvvury,et al.  Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes , 1995, Proceedings of International Electron Devices Meeting.

[37]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[38]  S. Selberherr Analysis and simulation of semiconductor devices , 1984 .

[39]  Jason C. S. Woo,et al.  Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis , 2002 .

[40]  P. Yang,et al.  Design for reliability: the major challenge for VLSI , 1993, Proc. IEEE.

[41]  G. Notermans,et al.  Pitfalls when correlating TLP, HBM and MM testing , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[42]  C.C. Russ,et al.  Wafer cost reduction through design of high performance fully silicided ESD devices , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[43]  Kaustav Banerjee,et al.  Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs , 2002 .

[44]  Kartikeya Mayaram,et al.  Self-heating effects in basic semiconductor structures , 1993 .

[45]  G. Groeseneken,et al.  Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[46]  Jeremy C. Smith An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[47]  C. R. Crowell The Richardson constant for thermionic emission in Schottky barrier diodes , 1965 .

[48]  D. S. Campbell,et al.  Thermal failure in semiconductor devices , 1990 .

[49]  Katsuhiko Kubota,et al.  Photon emission study of ESD protection devices under second breakdown conditions , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[50]  J. Woo,et al.  Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation , 2002 .

[51]  J. P. Krusius,et al.  Series resistance of silicided ohmic contacts for nanoelectronics , 1992 .

[52]  Amitava Chatterjee,et al.  Hot-electron reliability and ESD latent damage , 1988 .

[53]  R. Stratton,et al.  Field and thermionic-field emission in Schottky barriers , 1966 .

[54]  A. Amerasekera,et al.  Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /spl mu/m CMOS process , 1996, International Electron Devices Meeting. Technical Digest.

[55]  Chenming Hu,et al.  Temperature and current effects on small-geometry-contact resistance , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[56]  Richard C. Jaeger,et al.  Temperature dependent threshold behavior of depletion mode MOSFETs: Characterization and simulation☆ , 1979 .

[57]  R. Moss Caution-Electrostatic Discharge at Work! , 1982 .

[58]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .

[59]  M. Green Intrinsic concentration, effective densities of states, and effective mass in silicon , 1990 .

[60]  Charvaka Duvvury Issues in Deep Submicron State-of-the-Art ESD Design , 2001, ISQED.

[61]  P. Niles,et al.  Diffused resistors characteristics at high current density levels-analysis and applications , 1989 .

[62]  Kaustav Banerjee,et al.  Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors , 2002 .

[63]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[64]  Guido Groeseneken,et al.  Influence of gate length on ESD-performance for deep sub micron CMOS technology , 1999 .

[65]  J.C. Smith A substrate triggered lateral bipolar circuit for high voltage tolerant ESD protection applications , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[66]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[67]  Kaustav Banerjee,et al.  Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[68]  M. Ieong,et al.  Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[69]  Ching-Yuan Wu,et al.  A self-consistent characterization methodology for Schottky-barrier diodes and ohmic contacts , 1994 .

[70]  S. Voldman The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling , 1999 .

[71]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[72]  Changhoon Choi Modeling of nanoscale mosfets , 2002 .