Operation of logic function in a Coulomb blockade device

This letter presents the experimental demonstration of a Coulomb blockade (CB) logic device. Our logic architecture consists of an array of current pathways, controlled by CB switching nodes. In this architecture, high gain is not required to transmit information, making it well suited to the CB device. Each CB node is switched between a blockaded state and a completely pinched-off state, minimizing the influence of stray potentials. Using a multi-phase clocking scheme to precisely control electron flow, the AND logic function is observed using as few as 160 electrons.

[1]  John M. Martinis,et al.  Accuracy of electron counting using a 7‐junction electron pump , 1996 .

[2]  M. Ancona.  Design of computationally useful single-electron digital circuits , 1996 .

[3]  Kazuo Nakazato,et al.  Single-electron memory , 1993 .

[4]  Michel Devoret,et al.  Single-Electron Pump Based on Charging Effects , 1992 .

[5]  Michel Devoret,et al.  Single Charge Tunneling , 1992 .

[6]  Yoshihito Amemiya,et al.  Single-electron logic device based on the binary decision diagram , 1997 .

[7]  Stephen Y. Chou,et al.  Silicon single-electron quantum-dot transistor switch operating at room temperature , 1998 .

[8]  K. Likharev.  Single-electron transistors: Electrostatic analogs of the DC SQUIDS , 1987 .

[9]  C. Lent,et al.  Demonstration of a six-dot quantum cellular automata system , 1998 .

[10]  J. E. Mooij,et al.  Fabrication of multilayer single‐electron tunneling devices , 1995 .

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  Smith,et al.  Conductance oscillations periodic in the density of a one-dimensional electron gas. , 1989, Physical review letters.

[13]  K. Nakazato,et al.  Two-way switching based on turnstile operation , 1998 .

[14]  Sandip Tiwari,et al.  A silicon nanocrystals based memory , 1996 .

[15]  Electron pump current by two pulses with phase delay , 1997 .

[16]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.