Performance Analysis of Sliding Window Turbo Decoding Algorithms for 3GPP FDD Mode

In this paper we analyze the performance of a turbo decoder using two sliding window algorithms for the frequency division duplex (FDD) mode of the Third Generation Partnership Project (3GPP) standard. Focusing on the solution for the user equipment, we compare fixed-point realizations of the sliding window algorithms in terms of the computational complexity and memory requirements. We show that the bit and frame error rate performance of the sliding window scheme strongly depends on the guard window size. Furthermore, simulation results indicate that relatively small guard window sizes can significantly decrease the iteration gain for large frames. Finally, optimization of the windowing parameters achieves the desired trade-off between the performance degradation introduced by a windowing approach and the computational complexity and memory utilization.