Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs
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Library based design and IP reuse have been previouslyproposed to speed up the synthesis for large-scale FPGAdesigns. However, previous library based design flow faces severalunresolved challenges. Firstly, there may result in large wastearea between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce thewaste area, pre-synthesis each module for different ratios is timeconsuming and would require a large library. Secondly, when thetargeting FPGA architecture changes, a new library is needed tobest fit the targeting architecture. Re-synthesizing the library fordifferent architectures is not feasible. To address these challenges, we propose a dynamic module partitioning approach for thelibrary based design flow to dynamically generate the appropriateshape of modules based on single-ratio modules in the librarywhile efficiently utilizing the pre-placement module information. A set of rules are developed to select the most suitable moduleand determine the partition to minimize the area and delay ofthe placement without increasing much of the synthesis time. Theproposed approach can adapt to different architectures and alsoaddress the fixed-outline constraint. Experiment results show thatour approach can reduce the area by up to 10% with reasonablyincreased delay under acceptable runtime.
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