Implementation of RF communication subsets on common low frequency clocked FPGA
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Etienne Perret | David Hely | Nicolas Barbot | Romain Siragusa | Maxime Bernier | Mosabbah Mushir Ahmed | Frederic Garet
[1] Fernando Silveira,et al. Design optimization of a CMOS RF detector , 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).
[2] Zhuan Ye,et al. An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[3] Jin-Ku Kang,et al. A CMOS clock and data recovery with two-XOR phase-frequency detector circuit , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[4] Hiroshi Harada. A small-size software defined cognitive radio prototype , 2008, 2008 IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications.
[5] Arnaldo S. R. Oliveira,et al. Agile All-Digital RF Transceiver Implemented in FPGA , 2017, IEEE Transactions on Microwave Theory and Techniques.