A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain

This brief proposes a 0.25V rail-to-rail three stage OTA. The proposed OTA improves a DC gain by inserting an NMOS gate-driven amplifier into the conventional bulk-driven OTA. In addition, it uses an asymmetric self-cascode transistor and an indirect feedback compensation to enhance a DC gain and an unit-gain frequency. At the first stage, the bulk-driven amplifier has a rail-to-rail input, but it has a low DC gain due to a small transconductance. At the second stage, the NMOS gate-driven amplifier enhances the DC gain. At the last stage, the common-source amplifier drives an output load capacitor. The proposed OTA was fabricated using a 65nm CMOS process. Its area is 0.002mm2. It consumes $0.026~\mu \text{W}$ at the supply-voltage of 0.25V. The DC gain and unit-gain frequency are 70dB and 9.5kHz, respectively, with the phase margin of 88° at the load capacitance of 15pF.

[1]  Sameer R. Sonkusale,et al.  A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Ki-Chan Woo,et al.  A-250mV supply-voltage 65dB-gain OTA with an enhanced bandwidth and a reduced compensation-capacitor , 2018, 2018 International Conference on Electronics, Information, and Communication (ICEIC).

[3]  Carlos Galup-Montoro,et al.  Series-parallel association of FET's for high gain and high frequency applications , 1994, IEEE J. Solid State Circuits.

[4]  V. Saxena,et al.  Indirect feedback compensation of CMOS op-amps , 2006, 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED '06..

[5]  D. Flandre,et al.  Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors , 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

[6]  Farshad Moradi,et al.  Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Antonio Torralba,et al.  0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Akihiro Tanaka,et al.  0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Yehya H. Ghallab,et al.  A 0.4-V Miniature CMOS Current Mode Instrumentation Amplifier , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Xu Shiliu,et al.  High DC gain self-cascode structure of OTA design with bandwidth enhancement , 2016 .

[11]  Alessandro Trifiletti,et al.  0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Fabian Khateb,et al.  Design and Implementation of a 0.3-V Differential Difference Amplifier , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.