Chapter 7 – Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors

Publisher Summary This chapter explores different trade-offs for processing element topologies based on an analytical framework and IPv4 benchmark. A different partitioning for the benchmark on the IXP1200 is implemented. The employed analytical performance modeling is suited to exploring the design space for network processors, because it is quite accurate compared to full system simulation—apart from alleviating the need for detailed executable models and packet traces. For performance metrics, pipelined topologies are found to be consuming more local data memory and causing more end-to-end delay, although they have only point-to-point connections. For forwarding applications, pool topology is the most flexible from a programmability and scalability point of view, as well as best performing for the chosen metrics. The preciseness and usefulness of the analytical framework compared to a detailed simulation of the system are verified.

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