A family of third-generation compacted arrays with up to 237 K gates has been developed using a channelless architecture. 1- mu m HCMOS (high-speed complementary metal-oxide semiconductor) technology with 0.75- mu m effective channel length was used to fabricate the device. Complex designs with up to 100 K utilized gates can be implemented on a single chip using this technology. Switching performance of 400 ps is achieved on two input NAND gates with typical loading.<<ETX>>