Low Dose-Rate, High Total Dose Set-Up for Rad-Hard CMOS I/O Circuits Testing

In this paper, the planning of low dose-rate, high total dose testing campaign for I/O circuits is reported. In particular, the paper describes all development steps, starting from the rad-hard I/O circuits design and the implementation of the test-chip, which is meant to allow comparative testing between rad-hard and standard devices. The designed experimental setup permits in situ measurements, therefore the circuits behavior can be remotely monitored for very long periods. This feature enables low dose-rate testing up to very high dose.