A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems

In multitasking, priority-driven systems, resource access-control protocols such as Priority Ceiling Protocol (PCP) reduce the undesirable effects of resource contention. In general, software implementation of these protocols entails costly computations that can degrade the system performance to unacceptable levels. In this paper, we present the design for a hardware-accelerator to execute the PCP functionality for controlling access to multiple-unit resources and illustrate that the proposed implementation accelerates the execution time by a factor of up to 30.

[1]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[2]  Bruce Jacob,et al.  Hardware support for real-time operating systems , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[3]  Yudong Tan,et al.  A novel parallel deadlock detection algorithm and architecture , 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).

[4]  Ference Belik.  An Efficient Deadlock Avoidance Rechnique , 1990, IEEE Trans. Computers.

[5]  Jean J. Labrosse,et al.  MicroC/OS-II: The Real Time Kernel , 1998 .

[6]  Lui Sha,et al.  Priority Inheritance Protocols: An Approach to Real-Time Synchronization , 1990, IEEE Trans. Computers.

[7]  I. Cahit.  Deadlock detection using (0, 1)-labelling of resource allocation graphs , 1998 .

[8]  Henrik Thane,et al.  Hardware support for priority inheritance , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.