A Programmable Vector Coprocessor Architecture for Wireless Applications

The physical layers of most wireless protocols are traditionally implemented in ASICs due to the heavy computation requirements. These solutions are costly to design and hardwired solutions that offer no post-programmability. In this paper, we introduce a flexible coprocessor architecture customized for wireless protocols. To accomplish the design, a complete baseband physical layer for the 802.11b and Hiperlan2 protocols was developed and the computational characteristics of the time-critical code analyzed. In particular, we studied the behavior of the Viterbi decoding stage and the FIR filter. We propose an fully programmable vector coprocessor architecture that achieves real-time performance for these computation-heavy algorithms. The design consists of a memory streaming macro-pipelined vector architecture that effectively exploits the high degree of data-level parallelism within these algorithms. It offers high performance while maintaining full programmability.

[2]  Gerhard Fettweis,et al.  Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications , 2002 .

[3]  Joseph R. Cavallaro,et al.  A programmable baseband processor design for software defined radios , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[4]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[5]  Michael Rice,et al.  Digital receivers and transmitters using polyphase filter banks for wireless communications , 2003 .

[6]  Ran-Hong Yan,et al.  A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  Christoforos E. Kozyrakis,et al.  Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks , 2002, MICRO.

[8]  Teresa H. Meng,et al.  A 140-Mb/s, 32-state, radix-4 Viterbi decoder , 1992 .

[9]  Steven W. Smith,et al.  The Scientist and Engineer's Guide to Digital Signal Processing , 1997 .

[10]  Dong Sam Ha,et al.  A low-power Viterbi decoder design for wireless communications applications , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[11]  David A. Patterson,et al.  Scalable Vector Media-processors for Embedded Systems , 2002 .

[12]  Venkatesh Akella,et al.  Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[13]  H. Meyr,et al.  High-speed parallel Viterbi decoding: algorithm and VLSI-architecture , 1991, IEEE Communications Magazine.

[14]  John G. Proakis,et al.  Digital Communications , 1983 .

[15]  David Seal,et al.  ARM Architecture Reference Manual , 2001 .

[16]  Gerald H. Hilderink,et al.  Parallel Processing — the picoChip way! , 2003 .

[17]  William J. Dally,et al.  Evaluating the Imagine stream architecture , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..