Design of memristor based low power and highly reliable ReRAM cell

A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell.

[1]  Jae Hyuck Jang,et al.  Atomic structure of conducting nanofilaments in TiO2 resistive switching memory. , 2010, Nature nanotechnology.

[2]  Ping Keung Ko,et al.  A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation , 1997 .

[3]  Saurabh Chaudhury,et al.  Advantage of CNTFET characteristics over MOSFET to reduce leakage power , 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

[4]  A. WulfWm.,et al.  Hitting the memory wall , 1995 .

[5]  Malgorzata Chrzanowska-Jeske,et al.  Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes , 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

[6]  H.-S. Philip Wong,et al.  Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  Soumitra Pal,et al.  Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[9]  Sung-Mo Kang,et al.  Field Programmable Stateful Logic Array , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[11]  Khaled N. Salama,et al.  Memristor-based memory: The sneak paths problem and solutions , 2013, Microelectron. J..

[12]  Charles M. Lieber,et al.  Nanoelectronics from the bottom up. , 2007, Nature materials.

[13]  Baker Mohammad,et al.  Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Mohammad A. Ahmed,et al.  Logical Effort model for CNFET circuits with CNTs variations , 2015, 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO).

[15]  Mohd. Hasan,et al.  Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory , 2017, Microelectron. J..

[16]  Keivan Navi,et al.  Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic , 2015, IET Circuits Devices Syst..

[17]  Jan M. Rabaey,et al.  Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration , 2018, IEEE Journal of Solid-State Circuits.

[18]  Ligang Gao,et al.  High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm , 2011, Nanotechnology.

[19]  Jörg Appenzeller,et al.  Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.

[20]  Ping Tang,et al.  A Sensor Specified Method Based on Spectral Transformation for Masking Cloud in Landsat Data , 2013, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing.

[21]  Comparative Analysis of Ti, Ni, and Au Electrodes on Characteristics of TiO2 Nanofibers for Humidity Sensor Application , 2013 .

[22]  I. Filanovsky,et al.  Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits , 2001 .

[23]  Aminul Islam,et al.  TG based 2T2M RRAM using Memristor as Memory Element , 2016 .

[24]  Rajiv V. Joshi,et al.  An Energy-Efficient Digital ReRAM-Crossbar-Based CNN With Bitwise Parallelism , 2017, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

[25]  Luigi Fortuna,et al.  A chaotic circuit based on Hewlett-Packard memristor. , 2012, Chaos.

[26]  From carbon atom to graphene on Cu(111): an ab-initio study , 2015 .

[27]  G. I. Meijer,et al.  Who Wins the Nonvolatile Memory Race? , 2008, Science.

[28]  L. Chua.  Memristor-The missing circuit element , 1971 .

[29]  K. Roy,et al.  Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability , 2006, IEEE Transactions on Electron Devices.

[30]  Meng-Fan Chang,et al.  Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications , 2012, IEEE Journal of Solid-State Circuits.

[31]  Jeyavijayan Rajendran,et al.  Leveraging Memristive Systems in the Construction of Digital Logic Circuits , 2012, Proceedings of the IEEE.

[32]  Tiago Ramalho,et al.  Simulation of stochastic network dynamics via entropic matching. , 2012, Physical review. E, Statistical, nonlinear, and soft matter physics.

[33]  Fabrizio Lombardi,et al.  Device Model for Ballistic CNFETs Using the First Conducting Band , 2008, IEEE Design & Test of Computers.

[34]  G. M. Huang,et al.  Memristors for non-volatile memory and other applications , 2014 .

[35]  Soumitra Pal,et al.  Variation resilient low-power memristor-based synchronous flip-flops: design and analysis , 2018 .

[36]  Qiang Xu,et al.  A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[37]  Wei D. Lu,et al.  Data Clustering using Memristor Networks , 2015, Scientific Reports.

[38]  Massimiliano Di Ventra,et al.  Memristive model of amoeba learning. , 2008, Physical review. E, Statistical, nonlinear, and soft matter physics.

[39]  Kyungmin Kim,et al.  Memristor Applications for Programmable Analog ICs , 2011, IEEE Transactions on Nanotechnology.

[40]  D. Biolek,et al.  Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors , 2013, 1307.2717.

[41]  Marisa López-Vallejo,et al.  On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits , 2017, IEEE Transactions on Nanotechnology.

[42]  Aminul Islam,et al.  Comparative study of subthreshold leakage in CNFET & MOSFET @ 32-nm technology node , 2016, 2016 International Conference on Microelectronics, Computing and Communications (MicroCom).

[43]  Kaushik Roy,et al.  Leakage Power Analysis and Reduction for Nanoscale Circuits , 2006, IEEE Micro.

[44]  Mohd. Hasan,et al.  Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications , 2018 .

[45]  Soumitra Pal,et al.  9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue , 2016, IEEE Transactions on Device and Materials Reliability.

[46]  M. Pickett,et al.  A scalable neuristor built with Mott memristors. , 2013, Nature materials.

[47]  G. Subramanyam,et al.  A Memristor Device Model , 2011, IEEE Electron Device Letters.

[48]  V. A. Slipko,et al.  Complex dynamics and scale invariance of one-dimensional memristive networks. , 2012, Physical review. E, Statistical, nonlinear, and soft matter physics.

[49]  S. A. Abbasi,et al.  Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII , 2012, IEEE Transactions on Nanotechnology.

[50]  Sunil R. Das,et al.  Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[51]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[52]  P. McEuen,et al.  Single-walled carbon nanotube electronics , 2002 .

[53]  Paul A. Crowell,et al.  Using Programmable Graphene Channels as Weights in Spin-Diffusive Neuromorphic Computing , 2017, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

[54]  Yi Shen,et al.  Compound synchronization of four memristor chaotic oscillator systems and secure communication. , 2013, Chaos.

[55]  David J. Mountain,et al.  Memristor Crossbar Tiles in a Flexible, General Purpose Neural Processor , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[56]  Jan Reineke,et al.  Ascertaining Uncertainty for Efficient Exact Cache Analysis , 2017, CAV.

[57]  Haipeng Peng,et al.  Anti-synchronization for stochastic memristor-based neural networks with non-modeled dynamics via adaptive control approach , 2015 .

[58]  S. Durant.  Building Sustainable National Monitoring Networks , 2013 .

[59]  E. Lehtonen,et al.  Applications and limitations of memristive implication logic , 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.