CAD flows for chip-package coverification

A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification

[1]  Paul D. Franzon,et al.  Computer design strategy for MCM-D/flip-chip technology , 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

[2]  Joy Laskar,et al.  Review of RF packaging research at Georgia Tech's PRC , 1998, Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153).

[3]  Paul D. Franzon,et al.  Issues in partitioning integrated circuits for MCM-D/flip-chip technology , 1996, Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893).

[4]  T. Schaffer,et al.  A flip-chip implementation of the Data Encryption Standard (DES) , 1997, Proceedings 1997 IEEE Multi-Chip Module Conference.

[5]  Paul D. Franzon,et al.  Infrastructure and course progression for complex IC design education , 1999, Proceedings 1999 IEEE International Conference on Microelectronic Systems Education (MSE'99) 'Systems Education in the 21st Century' (Cat. No.99-63794).

[6]  P. Franzon,et al.  The NCSU design kit for IC fabrication through MOSIS , 1998 .

[7]  William D. Brown,et al.  Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects , 1999 .

[8]  Paul D. Franzon,et al.  System design optimization for MCM-D/flip-chip , 1995 .

[9]  W. E. Pence.  Packaging for wireless communications , 1994, Proceedings of 1994 IEEE Electrical Performance of Electronic Packaging.