UPPAAL Implementation Secrets

In this paper we present the continuous and on-going development of datastructures and algorithms underlying the verification engine of the tool UPPAAL. In particular, we review the datastructures of Difference Bounded Matrices, Minimal Constraint Representation and Clock Difference Diagrams used in symbolic state-space representation and -analysis for real-time systems.In addition we report on distributed versions of the tool, and outline the design and experimental results for new internal datastructures to be used in the next generation of UPPAAL.Finally, we mention work on complementing methods involving acceleration, abstraction and compositionality.

[1]  Wang Yi,et al.  Verification of an Audio Protocol with Bus Collision Using UPPAAL , 1996, CAV.

[2]  Gerd Behrmann,et al.  Efficient Guiding Towards Cost-Optimality in UPPAAL , 2001, TACAS.

[3]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[4]  Kim G. Larsen,et al.  Exact Acceleration of Real-Time Model Checking , 2002, Theory and Practice of Timed Systems @ ETAPS.

[5]  Cliff B. Jones,et al.  Tentative steps toward a development method for interfering programs , 1983, TOPL.

[6]  Stavros Tripakis,et al.  Kronos: A Model-Checking Tool for Real-Time Systems , 1998, CAV.

[7]  Kim G. Larsen,et al.  Model-checking real-time control programs: verifying LEGO MINDSTORMSTM systems using UPPAAL , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[8]  Wang Yi,et al.  Compositional and symbolic model-checking of real-time systems , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[9]  Kim G. Larsen,et al.  Scaling up Uppaal Automatic Verification of Real-Time Systems Using Compositionality and Abstraction , 2000, FTRTFT.

[10]  Wang Yi,et al.  Clock Difference Diagrams , 1998, Nord. J. Comput..

[11]  Henrik Reif Andersen,et al.  Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams , 2001, SMC@FLoC.

[12]  Sean R Eddy,et al.  What is dynamic programming? , 2004, Nature Biotechnology.

[13]  Kim G. Larsen,et al.  Formal Verification of a Power Controller Using the Real-Time Model Checker UPPAAL , 1999, ARTS.

[14]  K. Mani Chandy.  Parallel program design , 1989 .

[15]  David L. Dill,et al.  Timing Assumptions and Verification of Finite-State Concurrent Systems , 1989, Automatic Verification Methods for Finite State Systems.

[16]  Wang Yi,et al.  UPPAAL in 1995 , 1996, TACAS.

[17]  Stavros Tripakis,et al.  Model Checking of Real-Time Reachability Properties Using Abstractions , 1998, TACAS.

[18]  Wang Yi,et al.  Efficient Timed Reachability Analysis Using Clock Difference Diagrams , 1998, CAV.

[19]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[20]  Wang Yi,et al.  Compact Data Structures and State-Space Reduction for Model-Checking Real-Time Systems , 2003, Real-Time Systems.

[21]  Wang Yi,et al.  Compact Data Structure and State-Space Reduction for Model-Checking Real-Time Systems , 2003 .

[22]  Howard Wong-Toi,et al.  Symbolic approximations for verifying real-time systems , 1995 .

[23]  Conrado Daws,et al.  Two examples of verification of multirate timed automata with Kronos , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[24]  Wang Yi,et al.  Efficient verification of real-time systems: compact data structure and state-space reduction , 1997, Proceedings Real-Time Systems Symposium.

[25]  K. Mani Chandy,et al.  Parallel program design - a foundation , 1988 .

[26]  Kim Guldstrand Larsen,et al.  Model-Checking Real-Time Control Programs. Verifying LEGO Mindstorms Systems Using UPPAAL , 1999 .

[27]  Johan Bengtsson,et al.  Clocks, DBMS and States in Timed Systems , 2002 .

[28]  Wang Yi,et al.  Uppaal in a nutshell , 1997, International Journal on Software Tools for Technology Transfer.

[29]  Gerard J. Holzmann,et al.  On Limits and Possibilities of Automated Protocol Analysis , 1987, PSTV.

[30]  Wang Yi,et al.  UPPAAL - Now, Next, and Future , 2000, MOVEP.

[31]  Thomas Hune,et al.  Modeling a Language for Embedded Systems in Timed Automata , 2000 .

[32]  L. Thiele,et al.  Symbolic model checking of process networks using interval diagram techniques , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[33]  Mariëlle Stoelinga,et al.  Mechanical verification of the IEEE 1394a root contention protocol using Uppaal2k , 2001, International Journal on Software Tools for Technology Transfer.

[34]  Frits W. Vaandrager,et al.  Distributing Timed Model Checking - How the Search Order Matters , 2000, CAV.

[35]  Gerd Behrmann,et al.  A Performance Study of Distributed Timed Automata Reachability Analysis , 2002, PDMC@CONCUR.

[36]  Henning Dierks,et al.  Specification and verification of polling real time systems , 1999, Ausgezeichnete Informatikdissertationen.

[37]  Leslie Lamport,et al.  A fast mutual exclusion algorithm , 1987, TOCS.

[38]  Kim G. Larsen,et al.  Model Checking via Reachability Testing for Timed Automata , 1997, TACAS.

[39]  Tomas Rokicki.  Representing and modeling digital circuits , 1994 .

[40]  Susan Owicki,et al.  An axiomatic proof technique for parallel programs I , 1976, Acta Informatica.

[41]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[42]  H. Lonn,et al.  Formal verification of a TDMA protocol start-up mechanism , 1997, Proceedings Pacific Rim International Symposium on Fault-Tolerant Systems.

[43]  Henrik Reif Andersen,et al.  Difference Decision Diagrams , 1999, CSL.