Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔNIT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

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