Fan-Out Panel-Level Packaging (FOPLP)

All previously mentioned fan-out technologies are using the round 200 or 300 mm wafers as the temporary carriers for making the molds, RDLs, etc. (This is because of the existing equipment for fabricating the device wafers.) In order to increase the throughput, fan-out panel-level packaging (FOPLP) has been proposed.

[1]  J. Bauer,et al.  From wafer level to panel level mold embedding , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[2]  Steve Chiu,et al.  Development and characterization of new generation panel fan-out (P-FO) packaging technology , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[3]  Fumihiko Taniguchi,et al.  Advanced Embedded Packaging for Power Devices , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[4]  Naoki Hayashi,et al.  A novel Wafer level Fan-out Package (WFOP™) applicable to 50um pad pitch interconnects , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[5]  J. Bauer,et al.  Large area compression molding for Fan-out Panel Level Packing , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[6]  John H. Lau,et al.  Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration , 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.