A Novel Ultra-Compact FPGA PUF: The DD-PUF

In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGAcompatible PUFs.

[1]  Arslan Munir,et al.  PUF-RAKE: A PUF-Based Robust and Lightweight Authentication and Key Establishment Protocol , 2021, IEEE Transactions on Dependable and Secure Computing.

[2]  Erdinc Avaroglu,et al.  The implementation of ring oscillator based PUF designs in Field Programmable Gate Arrays using of different challenge , 2020 .

[3]  Máire O'Neill,et al.  A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs , 2019, Journal of Cryptographic Engineering.

[4]  Ulrich Rührmair,et al.  The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks , 2019, IACR Cryptol. ePrint Arch..

[5]  Debdeep Mukhopadhyay,et al.  Building PUF Based Authentication and Key Exchange Protocol for IoT Without Explicit CRPs in Verifier Database , 2019, IEEE Transactions on Dependable and Secure Computing.

[6]  Michael Pehl,et al.  Side-Channel Analysis of the TERO PUF , 2019, COSADE.

[7]  Steve R. Gunn,et al.  Lightweight PUF-Based Authentication Protocol for IoT Devices , 2018, 2018 IEEE 3rd International Verification and Security Workshop (IVSW).

[8]  Máire O'Neill,et al.  FPGA-based strong PUF with increased uniqueness and entropy properties , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[9]  Chongyan Gu,et al.  Improved Reliability of FPGA-Based PUF Identification Generator Design , 2017, ACM Trans. Reconfigurable Technol. Syst..

[10]  Mark Mohammad Tehranipoor,et al.  An Aging-Resistant RO-PUF for Reliable Key Generation , 2016, IEEE Transactions on Emerging Topics in Computing.

[11]  Debdeep Mukhopadhyay,et al.  A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications , 2015, IEEE Transactions on Multi-Scale Computing Systems.

[12]  Máire O'Neill,et al.  Ultra-compact and robust FPGA-based PUF identification generator , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[13]  Miodrag Potkonjak,et al.  Robust and flexible FPGA-based digital PUF , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[14]  Gang Qu,et al.  A highly flexible ring oscillator PUF , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Maire O'Neill,et al.  A unique and robust single slice FPGA identification generator , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[16]  Ulrich Rührmair,et al.  PUFs at a glance , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  Lilian Bossuet,et al.  A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon , 2014, IEEE Transactions on Emerging Topics in Computing.

[18]  Benedikt Heinz,et al.  Localized electromagnetic analysis of RO PUFs , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[19]  Chi-En Daniel Yin,et al.  Improving PUF security with regression-based distiller , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[20]  Chi-En Daniel Yin,et al.  Design and implementation of a group-based RO PUF , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Piedad Brox Jiménez,et al.  Reducing bit flipping problems in SRAM physical unclonable functions for chip identification , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[22]  Maximilian Hofer,et al.  Physical Unclonable Functions in Theory and Practice , 2012 .

[23]  Mitsugu Iwamoto,et al.  Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches , 2011, CHES.

[24]  Mario Konijnenburg,et al.  Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[25]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[26]  Jorge Guajardo,et al.  Extended abstract: The butterfly PUF protecting IP on every FPGA , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[27]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[28]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[29]  G. Edward Suh,et al.  Extracting secret keys from integrated circuits , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[31]  L. Reyneri,et al.  Oscillatory metastability in homogeneous and inhomogeneous flip-flops , 1990 .

[32]  G. Scotti,et al.  Title of the paper: SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing , 2020 .

[33]  Lilian Bossuet,et al.  Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  M. Tehranipoor,et al.  Aging Resistant RO PUF with Increased Reliability in FPGA , 2017 .

[35]  Ingrid Verbauwhede,et al.  Intrinsic PUFs from Flip-flops on Reconfigurable Devices , 2008 .