Design and Application of Power Optimized High-Speed CMOS Frequency Dividers

Frequencies in the gigahertz range translate switching activity and internal node capacitance quickly to high power values. Therefore, the power optimized design of high-speed CMOS logic-based frequency dividers is sensitive to circuit partitioning and selection of flip-flop-type and logic family. On the basis of two circuit examples, the design of highly power optimized dividers based on conventional CMOS logic is demonstrated. First, a divide-by-15 circuit based on sense-amplifier and master-slave flip-flops is discussed. A 5.5-GHz demonstrator implemented in a 90-nm low-power CMOS technology consumes only 190 muW/GHz for a supply voltage of 1.1 V. Second, an even faster CMOS divider concept without static power consumption, except leakage power, is proposed. The circuit divides an input signal by two and generates four phases with highly accurate phase skew of 90 deg. The maximum operation frequency is 11.6 GHz for a supply voltage of 1.5 V, slow process and worst case operation parameters. Higher frequencies can be achieved by a hybrid approach where the signal is first divided by a factor of two in a single current mode logic (CML) stage and then by the proposed circuit by another factor of two for the generation of the four phases. The divider is applied to dual modulus pre-scalers and IQ receivers. A variant of the circuit contains an intrinsic phase-rotator, allowing pre-scalers without any phase synchronization. Therewith, the power consumption is not only reduced due to the efficient divider implementation but also by a simplified architecture of the overall pre-scaler.

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