Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications
暂无分享,去创建一个
[1] Massoud Pedram,et al. Clock-gating and its application to low power design of sequential circuits , 2000 .
[2] Niraj K. Jha,et al. High-level synthesis of low-power control-flow intensive circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Luca Benini,et al. A scalable ODC-based algorithm for RTL insertion of gated clocks , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[4] Norbert Wehn,et al. Automating RT-level operand isolation to minimize power consumption in datapaths , 2000, DATE '00.
[5] Arvind,et al. Modular scheduling of guarded atomic actions , 2004, Proceedings. 41st Design Automation Conference, 2004..
[6] Sujit Dey,et al. A power management methodology for high-level synthesis , 1998, Proceedings Eleventh International Conference on VLSI Design.
[7] Arvind,et al. High-level synthesis: an essential ingredient for designing complex ASICs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[8] Massoud Pedram,et al. Low-power RT-level synthesis techniques: a tutorial , 2005 .
[9] Rainer Leupers,et al. Automatic ADL-based Operand Isolation for Embedded Processors , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[10] Saraju P. Mohanty,et al. A framework for energy and transient power reduction during behavioral synthesis , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] José C. Monteiro,et al. Scheduling techniques to enable power management , 1996, DAC '96.
[12] Srivaths Ravi,et al. Transient power management through high level synthesis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[13] James C. Hoe,et al. Hardware Synthesis from Term Rewriting Systems , 1999, VLSI.
[14] Sandeep K. Shukla,et al. Low-power hardware synthesis from TRS-based specifications , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..
[15] Gaurav Singh,et al. Algorithms for Low Power Hardware Synthesis from CAOS-- Concurrent Action Oriented Specifications , 2006 .
[16] Luca Benini,et al. Clock-tree power optimization based on RTL clock-gating , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).