Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design
暂无分享,去创建一个
[1] Oliver Schrape,et al. Implementation of DBFN processor for Synthetic Aperture Radar application , 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).
[2] Xin Fan,et al. Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Jiri Gaisler. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture , 2002, Proceedings International Conference on Dependable Systems and Networks.
[4] Robert C. Aitken,et al. Low Power Methodology Manual - for System-on-Chip Design , 2007 .
[5] Takayasu Sakurai,et al. Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs , 2010, TODE.
[6] Milos Krstic,et al. Design Flow for Radhard TMR Flip-Flops , 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.
[7] Aleksandar Simevski,et al. Comparative Analyses of Low-Power IC Design Techniques based on Chip Measurements , 2018, 2018 16th Biennial Baltic Electronics Conference (BEC).