Hardware-Oriented Models for VLSI Implementation of Self-Organizing Maps

In this work, two hardware-oriented models for the Self-Organizing Feature Map (SOFM) are introduced. The first model, based on a dot-product neuron, is suitable for analog VLSI implementations. For the second one, we choose minimal expressions, from the viewpoint of the digital VLSI, for the different aspects of the conventional SOFM, which lead to a digital-oriented SOFM. Both hardware-oriented models are verified by means of computer simulations. Finally, a SIMD coprocessor based on the digital SOFM introduced is designed and simulated by means of a well known hardware description language, VHDL.