Simultaneous Optimization of Delay and Number of Operations in Multiplierless Implementation of Linear Systems

The problem of implementing linear systems in hardware by efficiently using shifts and additions instead of multiplications has been actively researched in the past. Most of the works have concentrated on reducing the number of operations by using different techniques for redundancy elimination and have not considered their effect on the delay of the transformed computations. In this paper, we present a methodology that reduces the number of operations as much as possible by using common subexpression elimination, and at the same time, controls the critical path of the computations. To the best of our knowledge this method is the first one that controls delay while extracting recursive common subexpressions. Our method is fast and can be used in linear systems involving any number of variables. Experimental results show a very marginal increase in the number of operations over the algorithm that only performs redundancy elimination and an average reduction of 45% in the number of additions compared to a method that only extracts non-recursive common subexpressions. Index Terms – delay optimization, common subexpression elimination, DSP transforms, multiplierless filters, logic synthesis