A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator

This paper presents the design of fully differential second-order delta-sigma modulator. A current feedback technique is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance and to improve the transmission error in the memory cell. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. In this paper, the SDM is simulated with TSMC 0.35 micrometre CMOS process technology. The simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 75 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 16 mW.

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