Subthreshold MOS implementation of neural networks with on-chip error backpropagation learning

Subthreshold analog circuits for MOS implementation of artificial neural networks are presented with on-chip learning capability. Each synapse circuits consist of a storage capacitor and 3 analog multiplier, i.e. one for signal feedforward, one for outer-product synaptic weight adjustments, and one for error backpropagation. While all the 3 multipliers are used for error backpropagation learning, only the first 2 multipliers are used for Hebbian learning. Each neuron circuits are composed of a sigmoid circuit and a sigmoid derivative circuit, which show near ideal sigmoid characteristics and provide external gain-control capability. All the circuits incorporate modular architecture, and are designed to increase the numbers of neurons and layers with multiple chips. Also, the subthreshold operation provides low power consumption and large scale implementation.