We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.
[1]
Alberto L. Sangiovanni-Vincentelli,et al.
Interface-based design
,
1997,
DAC.
[2]
Hugo De Man,et al.
Operating system based software generation for systems-on-chip
,
2000,
Proceedings 37th Design Automation Conference.
[3]
Luciano Lavagno,et al.
Hardware-Software Co-Design of Embedded Systems
,
1997
.
[4]
Luciano Lavagno,et al.
Hardware-software co-design of embedded systems: the POLIS approach
,
1997
.
[5]
T.A.C.M. Claasen.
High speed: not the only way to exploit the intrinsic computational power of silicon
,
1999,
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[6]
Heinrich Meyr,et al.
A framework for fast hardware-software co-simulation
,
2001,
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[7]
Daniel D. Gajski,et al.
SPECC: Specification Language and Methodology
,
2000
.