A Method to Design SEC-DED-DAEC Codes With Optimized Decoding

Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes have been proposed to protect SRAM devices from multiple cell upsets (MCUs). The correction of double adjacent errors ensures that the most common types of MCUs are corrected. At the same time, SEC-DED-DAEC codes require the same number of parity check bits as traditional SEC-DED codes. The main overhead associated with SEC-DED-DAEC codes is the increase in decoding complexity that can impact access time and circuit power and area. In this paper, a method to design SEC-DED-DAEC codes with optimized decoding is presented and evaluated. The proposed scheme starts by setting some constraints on the parity check matrix of the codes. Those constraints are then used to simplify the decoding. The proposed scheme has been implemented and evaluated for different word-lengths. The results show that, for data words of 32 bits, the scheme can be implemented with the same number of parity check bits as SEC-DED codes. For 16 and 64 bits words, an additional parity check bit is required, making the scheme less attractive. With the proposed method, the decoders can be optimized for area or speed. Both implementations are evaluated and compared with existing SEC-DED-DAEC decoders. The results show that the proposed decoders reduce significantly the circuit area, power, and delay.

[1]  J. Draper,et al.  Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[2]  Nur A. Touba,et al.  Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[3]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[4]  Michael Gössel,et al.  New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[5]  Shi-Jie Wen,et al.  Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Marco Ottavi,et al.  A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Xiaoxuan She,et al.  SEU Tolerant Memory Using Error Correction Code , 2012, IEEE Transactions on Nuclear Science.

[8]  Sanghyeon Baeg,et al.  Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance , 2010, IEEE Transactions on Nuclear Science.

[9]  Y. Tosaka,et al.  Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's , 2000, IEEE Electron Device Letters.

[10]  Avijit Dutta,et al.  Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[11]  M. Sachdev,et al.  A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory , 2013, IEEE Transactions on Device and Materials Reliability.

[12]  Marco Ottavi,et al.  Low-cost single error correction multiple adjacent error correction codes , 2012 .

[13]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[14]  L. Litwin,et al.  Error control coding , 2001 .

[15]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[16]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..