Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options

Data transfer and storage issues "take the centre stage" in information and communication systems because of the increasing complexity and data dominance typically associated to them. In this paper, we summarise a systematic methodology for the power critical storage modules such as local SRAMs. We focus on their memory organisation (access schedule and data assignment) together with an exploration of the effect that the interconnect technology may have on the energy consumed by these local memory organisations in deep sub-micron technologies.

[1]  Hugo De Man,et al.  Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[2]  Diederik Verkest,et al.  Global multimedia system design exploration using accurate memory organization feedback , 1999, DAC '99.

[3]  Vinod K. Agarwal,et al.  The Effect of Technology Scaling on Microarchitectural Structures , 2000 .

[4]  Erik Brockmeyer,et al.  Layer assignment techniques for low energy in multi-layered memory organisations , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Hua Wang,et al.  A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[6]  Erik Brockmeyer,et al.  Data Access and Storage Management for Embedded Programmable Processors , 2002, Springer US.

[7]  George Lawton Storage Technology Takes Center Sstage , 1999, Computer.

[8]  Mahmut T. Kandemir,et al.  Reducing memory requirements of nested loops for embedded systems , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Luca Benini,et al.  Memory design techniques for low energy embedded systems , 2002 .

[10]  Erik Brockmeyer,et al.  Storage Management Programmable Process , 2002 .

[11]  Erik Brockmeyer,et al.  Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[12]  Hugo De Man,et al.  Global interconnect trade-off for technology over memory modules to application level: case study , 2003, SLIP '03.

[13]  Dennis Sylvester,et al.  Impact of small process geometries on microarchitectures in systems on a chip , 2001 .

[14]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[15]  Erik Brockmeyer,et al.  Layer assignment techniques for low power in multi-layered memory organisations. , 2003 .

[16]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[17]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[18]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[19]  Mahmut T. Kandemir,et al.  Improving Cache Locality by a Combination of Loop and Data Transformation , 1999, IEEE Trans. Computers.

[20]  Luca Benini,et al.  SDRAM-Energy-Aware memory allocation for dynamic multi-media applications on multi-processor platforms , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[21]  Rudy Lauwereins,et al.  Data reuse exploration techniques for loop-dominated applications , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[22]  Alexandru Nicolau,et al.  Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration , 1998 .

[23]  Erik Brockmeyer,et al.  Data and memory optimization techniques for embedded systems , 2001, TODE.

[24]  Erik Brockmeyer,et al.  Data reuse analysis technique for software-controlled memory hierarchies , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[25]  Francky Catthoor,et al.  Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design , 1998 .