Optimizing inter-FPGA communication by automatic channel adaptation

Tightly coupled multi-FPGA architectures gain more and more interest in various application areas, like prototyping MPSoC, code breaking, or artificial neural networks, just to name a few. Communication protocols and implementations have to deal with rising clock frequencies on the one hand and short time to market demands on the other hand. These tight schedules and limited routing areas often lead to PCB routing which is not ideal in terms of length matching and therefore introduces different delays in parallel transmission lines. Crosstalk, impedance mismatch, and jitter further deteriorate the quality of the received signal. In order to achieve optimum data rates modern FPGAs offer different mechanisms to adapt to the behavior of the channel. This paper introduces a communication protocol and an architecture which evaluates the channel delays and automatically generates the configuration for the different mechanisms offered by the used FPGAs. The protocol supports several transmission standards and can be scaled to different physical and virtual channel widths.