Managing leakage power and reliability in hot chips using system floorplanning and SRAM design

Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). An increase in temperature also increases the probability of errors such as read/write errors or unstable memory accesses. In a thermal unaware paradigm, SRAM designers increase (overdrive) the supply voltage (Vdd) to increase their reliability. However, increasing Vdd in turn increases the memorypsilas leakage and dynamic power dissipation and its temperature is elevated. Thus Vdd, power, temperature, and probability of errors influence each other mutually and must be considered during SRAM design. This paper addresses two issues: (i) we propose a novel system level leakage aware floorplanner which optimizes floorplans for thermal-aware leakage power along with the traditional metrics of area and wire length; and (ii) we demonstrate the effect of temperature on the probability of errors of SRAM memories which helps designers select a thermal-aware operating voltage for SRAMs. We will also discuss temperaturehArrleakage positive feedback loop. We applied our floorplanner on eight industrial SoC designs from Freescale Semiconductor Inc. and we observed up to 135% difference in the leakage power between leakage-unaware and leakage aware floorplanning. In this paper we also quantify the effect of temperature on the probability of failures in memories. We observed that by considering the effect of temperature on memories, reducing Vdd can help improve both the reliability and the power dissipation. For a predefined limit on reliability, thermal aware Vdd selection can reduce the total power dissipation by up to 2.5X.