Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols

Using an analytical program model, we compare the memory-access penalty of five write-invalidate cache coherence protocols. The memory-access penalty is the average time that a processor is blocked per memory reference to shared writable blocks because of a miss or of coherence activity. The protocols are compared for two systems with different cache-to-cache and memory-to-cache transfer times. The model permits rapid evaluation of protocols for different environments.