Minimal Test Coverage of SSFs for the Majority Voters of TMR Configuration

In the current semiconductor technology evolution, reliability is a primary concern especially for the applications like banking, defense, medical, etc. To improve the reliability, redundancy techniques are most commonly used by means of either in hardware, software, time or information. Once the correctly designed circuit is manufactured, there must a testing procedure to check there are no flaws. Here, the importance of hardware redundancy to enhance the reliability and testing to verify the designs are explored. This study mainly deals with exhaustive single stuck-at fault coverage of majority voters (MV) of triple modular redundancy (TMR) configuration which in turn helps to mitigate single event upset (SEU) errors. In total, there are eight different majority voters of TMR configuration are analyzed, and a minimal test set is obtained in each voter circuits. In this paper, theoretical study conveys that the majority voter circuits namely MV4, MV5, MV5, MV6, MV7 and MV8 produce a minimal test covering all faults.

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