Pareto Analysis with Uncertainty

Pareto analysis is a broadly applicable method to model and analyze tradeoffs in multi-objective optimization problems. The set of Pareto optimal solutions is guaranteed to contain the best solution for any arbitrary cost function or selection procedure. This work introduces a method to explicitly take uncertainty into account during Pareto analysis. A solution is not modeled by a single point in the solution space, but rather by a set of such points. This is useful in settings with much uncertainty, such as during model-based design space exploration for embedded systems. A bounding-box abstraction is introduced as a finite representation of Pareto optimal solutions under uncertainty. It is shown that the set of Pareto optimal solutions in the proposed approach still captures exactly the potentially best solutions for any cost function as well as any way of reducing the amount of uncertainty. During model-based design space exploration, for instance, design and implementation choices that are made during the development process reduce the amount of uncertainty. Steps in such a refinement trajectory can render previously Pareto optimal solutions sub optimal. The presented results provide a way to ensure that early selections in the refinement process remain valid.

[1]  Wang Yi,et al.  UPPAAL 4.0 , 2006, Third International Conference on the Quantitative Evaluation of Systems - (QEST'06).

[2]  Jon C. Helton,et al.  Summary from the epistemic uncertainty workshop: consensus amid diversity , 2004, Reliab. Eng. Syst. Saf..

[3]  Manfred Broy,et al.  Specification and development of interactive systems: focus on streams, interfaces, and refinement , 2001 .

[4]  Shengbing Jiang,et al.  Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Christian Haubelt,et al.  Accelerating design space exploration using Pareto-front arithmetics [SoC design] , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[6]  Marta Z. Kwiatkowska,et al.  A refinement-based process algebra for timed automata , 2005, Formal Aspects of Computing.

[7]  Hendrik Brinksma,et al.  On Verification Modelling of Embedded Systems , 2004 .

[8]  Michael S. Eldred,et al.  Perspectives on optimization under uncertainty: Algorithms and applications. , 2004 .

[9]  Jürgen Teich,et al.  Pareto-Front Exploration with Uncertain Objectives , 2001, EMO.

[10]  Kim G. Larsen,et al.  Timed I/O automata: a complete specification theory for real-time systems , 2010, HSCC '10.

[11]  Philipp Limbourg,et al.  Multi-objective Optimization of Problems with Epistemic Uncertainty , 2005, EMO.

[12]  Thomas A. Henzinger,et al.  Interface automata , 2001, ESEC/FSE-9.

[13]  Twan Basten,et al.  Model-Driven Design-Space Exploration for Embedded Systems: The Octopus Toolset , 2010, ISoLA.

[14]  Christian Haubelt,et al.  Accelerating design space exploration using pareto-front arithmetics , 2003, ASP-DAC '03.

[15]  Twan Basten,et al.  An algebra of Pareto points , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).