Robust and energy-efficient DSP systems via output probability processing

This paper proposes to employ error statistics of nanoscale circuit fabrics to design robust energy-efficient digital signal processing (DSP) systems. Architectural level error statistics are exploited to generate probability or the reliability of each output bit of a DSP kernel. The proposed technique is referred to here as bit-level a posteriori probability processing (BLAPP). Energy efficiency and robustness of a 2D discrete cosine transform (2D-DCT) image codec employing BLAPP is studied. Simulations in a commercial 45nm CMOS process show that BLAPP provides up to 14X improvement in robustness, and 25% power savings over conventional 2D-DCT codec design.

[1]  Naresh R. Shanbhag,et al.  Soft NMR: Exploiting statistics for energy-efficiency , 2009, 2009 International Symposium on System-on-Chip.

[2]  Vivek De,et al.  Sub-90 nm technologies-challenges and opportunities for CAD , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[3]  Jie Chen,et al.  A Probabilistic-Based Design Methodology for Nanoscale Computation , 2003, ICCAD 2003.

[4]  Vivek De,et al.  Sub-90nm technologies: challenges and opportunities for CAD , 2002, ICCAD 2002.

[5]  J. Neumann.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[6]  Rouwaida Kanj,et al.  System-level SRAM yield enhancement , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[7]  Naresh R. Shanbhag.  Reliable and energy-efficient digital signal processing , 2002, DAC '02.

[8]  Jan M. Rabaey,et al.  Workloads of the Future , 2008, IEEE Design & Test of Computers.

[9]  Keith A. Bowman,et al.  Resilient circuits — Enabling energy-efficient performance and reliability , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[10]  Kia Bazargan,et al.  The synthesis of combinational logic to generate probabilities , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[11]  D. Blaauw,et al.  Opportunities and challenges for better than worst-case design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Wen-Hsiung Chen,et al.  A Fast Computational Algorithm for the Discrete Cosine Transform , 1977, IEEE Trans. Commun..

[13]  Kaushik Roy,et al.  Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.