A SINGLE BIT ERROR DETECTION AND CORRECTION BASED ON THEMRC AND THE MP TECHNIQUES IN RRNS ARCHITECTURE

This paper presents some results on single error detection and correction based on the Redundant Residue Number System (RRNS).The proposed technique utilizes the Mixed Radix Conversion (MRC) and the Modulus Projection (MP) algorithms that significantly simplifies the error correction process for integers. The MP considerably reduces the computational steps and hardware architecture and further improve the processing speed. This results in a considerable improvement in the speed by  and tends to require about  less hardware resources in the proposed scheme when compared with the existing scheme used in this work. The proposed scheme is built on simple adders in the design of the architecture which saw a considerable improvement in both area and speed in as compared to the work by Yangyang et. al [6] which used ROMs and latches for the design of their architecture.

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