Eine digitale Emulationsplattform für pulscodierte neuronale Netze mit adaptiven Synapsengewichten

The simulation of pulse-coded neural networks for the evaluation of biology-oriented image processing performed on general-purpose computers, e. g. PCs or workstations, is still very time-consuming and inefficient. According to observations in the biology pulse-coded neural networks process information with pulses and are characterised by the ability to adapt themselves to outside stimuli during processing. This ability for adaptation is known as learning process. For the purpose of learning it is required that weights of network connections (synapses) between network elements (neurons) are able to alter dynamically. The main bottle-neck during the simulation is the sequential access to the memory of dynamic network parameters (membrane potential and adative synaptic weights). This memory access is necessary for the computation and update of the neuron states. In this thesis a novel architectural concept and the development of a digital emulation platform are introduced that is intended for the simulation acceleration of pulse-coded neural networks. This emulation platform represents the first experimental platform of a pulse-coded neuron model with adaptive synaptic weights for the integral image processing. The platform is distinguished by the evaluation of various network dynamics and by the provision of high flexibility for the implementation. The architecture of the emulation platform realises an efficient communication between the parallel computation of network topologies and neuron states and is based on an unreported hardware/software-system. This hardware/softwaresystem exploits on the one hand the data parallelism by providing multiple processing elements and on the other hand the functional parallelism by the realisation of a multi-processor system. The specific characteristic of the neuron model is that the detection of image features, e. g. spots and edges, is performed on the basis of adaptive synaptic weights. Because of the continuous adaptation of synaptic weights that has to be carried out during the simulation the bottle-necks of limited memory bandwidth and of necessary calculation steps are giving rise to a more negative impact on the simulation performance. These bottle-neck problems are solved by a distributed memory architecture and a parallel implementation of the numerical integration method required for the computation of neuron states. The work in this thesis reveals that the requirements on a digital emulation platform for pulse-coded neural networks are best met with programmable application specific integrated circuits in the form of FPGAs. The advantages of FPGA technolgies are cost effectiveness for prototype designs and flexibility due to reconfigurability. However, the main benefits offered by today’s FPGA technologies are the capability for very large scale integration circuits, adequate operation speed performance and the realisation of sufficiently usable memory bandwidth. In the context of this thesis a prototyping printed circuit board for the emualtion platform was manufactured that incorporates three FPGA devices of the type Virtex-II and VirtexII Pro from Xilinx. The parallel accessible memory for the digital emulation on the printed circuit board consists of six SDRAM devices and twelve SRAM devices that provide an overall memory bandwidth of 2.6 GB/s. The implemented architecture of the emulation platform operates at a frequency of 50 MHz. It is evaluated that the emulation platform achieves a maximum acceleration factor of 30 for a sparsely connected network and a maximum acceleration factor of 8 for a dense connected network compared to performed software simulations on a stand-alone Linux-PC (2.4 GHz Pentium-IV-Processor from Intel and 1 GB RAM of main memory).