Satisfiability Checking Using Boolean Expression Diagrams

In this paper we present an algorithm for determining satisfiability of general Boolean formulas which are not necessarily on conjunctive normal form. The algorithm extends the well-known Davis-Putnam algorithm to work on Boolean formulas represented using Boolean Expression Diagrams (BEDs). The BED data structure allows the algorithm to take advantage of the built-in reduction rules and the sharing of sub-formulas. Furthermore, it is possible to combine the algorithm with traditional BDD construction (using Bryant's APPLY-procedure). By adjusting a single parameter to the BedSat algorithm it is possible to control to what extent the algorithm behaves like the APPLY-algorithm or like a SAT-solver. Thus the algorithm can be seen as bridging the gap between standard SAT-solvers and BDDs. We present promising experimental results for 566 non-clausal formulas obtained from the multi-level combinational circuits in the ISCAS'85 benchmark suite and from performing model checking of a shift-and-add multiplier.

[1]  Dhiraj K. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

[2]  Mary Sheeran,et al.  A Tutorial on Stålmarck's Proof Procedure for Propositional Logic , 2000, Formal Methods Syst. Des..

[3]  C. A. J. van Eijk,et al.  Sequential equivalence checking without state space traversal , 1998, DATE.

[4]  Roberto Sebastiani Applying GSAT to Non-Clausal Formulas (Research Note) , 1994, J. Artif. Intell. Res..

[5]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[6]  Hector J. Levesque,et al.  A New Method for Solving Hard Satisfiability Problems , 1992, AAAI.

[7]  Enrico Giunchiglia,et al.  Applying the Davis-Putnam Procedure to Non-clausal Formulas , 1999, AI*IA.

[8]  Henrik Reif Andersen,et al.  Boolean Expression Diagrams , 2002, Inf. Comput..

[9]  Koen Claessen,et al.  SAT-Based Verification without State Space Traversal , 2000, FMCAD.

[10]  R. Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.

[11]  Armin Biere,et al.  Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking , 2000, CAV.

[12]  Armin Biere,et al.  Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs , 1999, CAV.

[13]  Hantao Zhang,et al.  SATO: An Efficient Propositional Prover , 1997, CADE.

[14]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[15]  Mary Sheeran,et al.  A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic , 1998, FMCAD.

[16]  Poul Frederick Williams,et al.  Formal Verification based on Boolean Expression Diagrams , 2001, Electronic Notes in Theoretical Computer Science.

[17]  Parosh Aziz Abdulla,et al.  Symbolic Reachability Analysis Based on SAT-Solvers , 2000, TACAS.

[18]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[19]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.

[20]  Henrik Reif Andersen,et al.  Equivalence checking of combinational circuits using Boolean expression diagrams , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[22]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[23]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[24]  R. Bryant Binary decision diagrams and beyond: enabling technologies for formal verification , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).