An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line

A wide-range delay-locked loop (DLL) with infinite phase shift and duty cycle control is presented. A voltage-controlled sawtooth delay line provides not only the delay control but also duty cycle control. The proposed DLL achieves infinite phase shift by using a single loop. Therefore, it has the benefits of good jitter and wide range compared with the conventional dual-loop DLL. The proposed DLL has been fabricated in a 0.18-mum CMOS process and the core area is 0.45 times 0.3 mm2. The measurement results show the proposed DLL operates from 50 MHz to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured peak-to-peak jitter is 11.1 ps and the power consumption is 6 mW.

[1]  Wonchan Kim,et al.  A dual-loop delay-locked loop using multiple voltage-controlled delay lines , 2001 .

[2]  Shen-Iuan Liu,et al.  A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm , 2007, IEEE Journal of Solid-State Circuits.

[3]  Yiu-Fai Chan,et al.  A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[4]  D. Inglis,et al.  A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs , 2002, IEEE Journal of Solid-State Circuits.

[5]  E. L. Hudson,et al.  A variable delay line PLL for CPU-coprocessor synchronization , 1988 .

[6]  John G. Maneatis.  PLL Based on Self-Biased Techniques , 1996 .

[7]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[8]  Hong-June Park,et al.  A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Fenghao Mu,et al.  Pulsewidth control loop in high-speed CMOS clock buffers , 2000, IEEE Journal of Solid-State Circuits.

[10]  Shen-Iuan Liu,et al.  A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle , 2004 .

[11]  Deog-Kyoon Jeong,et al.  An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance , 2000, IEEE Journal of Solid-State Circuits.

[12]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[13]  Hyung-Kyu Lim,et al.  A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL , 1997 .

[14]  Thomas H. Lee,et al.  A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[15]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[16]  Young-Soo Sohn,et al.  A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme , 2005, IEEE Journal of Solid-State Circuits.

[17]  Shen-Iuan Liu,et al.  A single-path pulsewidth control loop with a built-in delay-locked loop , 2005, IEEE J. Solid State Circuits.

[18]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[19]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.