Advances in BDD reduction using Parallel Genetic Algorithms

Binary Decision Diagrams (BDDs) have proved to be a powerful representation for Boolean functions. Particularly, they are a very useful data structure for the symbolic model checking of digital circuits and other nite state systems, as well as other problems. Nevertheless, the size of the BDD representation of these functions is highly dependent on the order of the function arguments, also called variables, and to nd such good ordering is an NP-Complete problem. Many heuristics have been proposed to solve this problem, as the depthrst traversal algorithm, one of the best known techniques, and the genetic algorithm found in [ 6]. In this paper, we present a improvement to them, through a parallel genetic algorithm, and compare its experimental results with those obtained from an interleaving-based implementation of the depthrst traversal algorithm, applying them to the ISCAS85 benchmark circuits.

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