Current sensing completion detection in dual-rail asynchronous systems

This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection.

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