Modeling of Power Supply Transients for EMI Compliance in Digital Systems

This paper addresses the modeling of power supply voltage transients in digital systems, in order to estimate the system’s tolerance to this disturbance, in order to demonstrate EMI/EMC standard compliance. Electrical simulation is extensively used to demonstrate the possibility of exploiting the duality between time excitation and delay response, for combinational CUT (Circuit Under Test). We refer this as the “accordion” effect. The proposed technique makes use of concepts derived from the VLV (Very Low Voltage) testing and VDD ramp testing techniques. Two regions of operation under ∆VDD voltage drop are defined through the threshold power supply voltage, VDDth, parameter. Electrical simulation supports the method, recently proposed, to perform fault simulation either by using faulty delays (defect size proportional to ∆VDD magnitude) in the CUT and nominal time excitation rate, or by using a fault-free CUT description and faster test application times. Furthermore, for sequential circuits it is shown that the tolerance to ∆VDD disturbances may be significantly lower than the one observed in combinational CUTs, due to de-synchronization effects in storage elements.

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