Data driving circuit and delay locked loop circuit

A data driving circuit and a delay locked loop circuit are provided to prevent the DLL from being unlocked by suppressing a delay variation due to a phase difference according to a mask signal. A data driving circuit receives a first data signal and a first clock signal and outputs a second data signal, which is delivered to a display panel. A data driver(40) samples the first data signal according to a second clock signal, converts the sampled result to an analog signal, and outputs the second data signal. A mask signal generator(20) generates a mask signal, which is turned on within a predetermined time from a changing timing of the second data signal. A DLL(Delay Locked Loop)(30) generates the second clock signal from the first clock signal. A delay exists between the first and second clock signals. The delay is changed by a phase difference between the first and second clock signals. A variation in the delay is suppressed by the mask signal.