A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.

[1]  R. Castello,et al.  A 2-dB noise figure 900-MHz differential CMOS LNA , 2001 .

[2]  P. Leroux,et al.  A 0.8 dB NF ESD-protected 9 mW CMOS LNA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  Pedro M. Figueiredo,et al.  The MOS capacitor amplifier , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  A. Ziel.  Noise in solid state devices and circuits , 1986 .

[5]  Mourad N. El-Gamal,et al.  Very low-voltage (0.8V) CMOS receiver frontend for 5 GHz RF applications , 2002 .

[6]  R.E. Lehmann,et al.  X-band monolithic series feedback LNA , 1985, IEEE Transactions on Electron Devices.

[7]  H.R. Rategh,et al.  A 5-GHz CMOS wireless LAN receiver front end , 2000, IEEE Journal of Solid-State Circuits.

[8]  T. Manku,et al.  Microwave CMOS-device physics and design , 1999, IEEE J. Solid State Circuits.

[9]  D.J. Comer,et al.  Using the weak inversion region to optimize input stage design of CMOS op amps , 2004, IEEE Trans. Circuits Syst. II Express Briefs.

[10]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[11]  Pietro Andreani,et al.  Noise optimization of an inductively degenerated CMOS low noise amplifier , 2001 .

[12]  U. Lott,et al.  A switched-LNA in 0.18 /spl mu/m CMOS for Bluetooth applications , 2003, 2003 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers..

[13]  Sudipto Chakraborty,et al.  A 5-6 GHz fully-integrated CMOS LNA for a dual-band WLAN receiver , 2002, Proceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573).

[14]  E. H. Westerwick.  A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[15]  A. Furukawa,et al.  A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch , 2001, IEEE J. Solid State Circuits.

[16]  Mourad N. El-Gamal,et al.  Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[17]  P. De Vita,et al.  A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA , 2001, IEEE J. Solid State Circuits.

[18]  W. Foley,et al.  A differential 2.4 GHz switched-gain CMOS LNA for 802.11b and Bluetooth , 2002, Proceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573).

[19]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.