READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution

3D-memory is one of promising applications in 3D-IC technology. With a 3D integration technology, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to its stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes error rate of the top layer largest among all layers. From a heat perspective, the lower dies would suffer from reliability problems since the lower dies are placed on top of logic die. The heat dissipation can more influence lower dies than upper dies. This creates unequal a reliability distribution for each layer in 3D-memories. A novel ECC organization scheme for 3D-memory to secure reliable operations under soft error rate (SER) profiles is introduced in this paper. The proposed scheme does not require additional redundant arrays. Instead, it utilizes unused spare columns of relatively reliable layer memories to store additional check-bits of less reliable layer memories. It forms a heterogeneous ECC organization across different layers which enhances ECC capabilities in less reliable layers. In addition, redundancy sharing scheme for yield enhancement can be implemented with the proposed scheme. Experimental results show that a memory with the proposed method can tolerate more than three times of a bit-error rate compared to the conventional memory.

[1]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[2]  T. May,et al.  Alpha-particle-induced soft errors in dynamic memories , 1979, IEEE Transactions on Electron Devices.

[3]  Robert C. Aitken,et al.  Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[4]  Qiang Xu,et al.  Yield enhancement for 3D-stacked memory by redundancy sharing across dies , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Tao Li,et al.  Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[6]  Nur A. Touba,et al.  Exploiting Unused Spare Columns to Improve Memory ECC , 2009, 2009 27th IEEE VLSI Test Symposium.

[7]  Jung Ho Ahn,et al.  CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Valentin Gherman,et al.  Programmable extended SEC-DED codes for memory errors , 2011, 29th VLSI Test Symposium.

[9]  Cheng-Wen Wu,et al.  An integrated ECC and redundancy repair scheme for memory reliability enhancement , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[10]  Yu-Jen Huang,et al.  Area and reliability efficient ECC scheme for 3D RAMs , 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

[11]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[12]  Luca Benini,et al.  Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Luca Benini,et al.  Design space exploration for 3D-stacked DRAMs , 2011, 2011 Design, Automation & Test in Europe.

[14]  Christos A. Papachristou,et al.  A low power memory cell design for SEU protection against radiation effects , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[15]  Song Liu,et al.  Hardware/software techniques for DRAM thermal management , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[16]  Nur A. Touba,et al.  Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  E. A. Wolicki,et al.  Single Event Upset of Dynamic Rams by Neutrons and Protons , 1979, IEEE Transactions on Nuclear Science.

[18]  Meng-Fan Chang,et al.  A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms , 2013, IEEE Journal of Solid-State Circuits.

[19]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[20]  Leon Lantz,et al.  Soft errors induced by alpha particles , 1996, IEEE Trans. Reliab..

[21]  Hsien-Hsin S. Lee,et al.  An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[22]  S. Simmons,et al.  A study on the VLSI implementation of ECC for embedded DRAM , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[23]  Zhen Wang,et al.  Hierarchical decoding of double error correcting codes for high speed reliable memories , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  Tino Heijmen,et al.  Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits , 2005, 11th IEEE International On-Line Testing Symposium.

[25]  Meng-Fan Chang,et al.  17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[26]  T. Heijmen,et al.  A Comprehensive Study on the Soft-Error Rate of Flip-Flops From 90-nm Production Libraries , 2007, IEEE Transactions on Device and Materials Reliability.

[27]  Cecilia Metra,et al.  Impact of Bias Temperature Instability on Soft Error Susceptibility , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  Avijit Dutta,et al.  Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[29]  Gabriel H. Loh,et al.  3D-Integrated SRAM Components for High-Performance Microprocessors , 2009, IEEE Transactions on Computers.

[30]  Young-Hyun Jun,et al.  A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.

[31]  Nanning Zheng,et al.  Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology , 2011, Microprocess. Microsystems.

[32]  So-Ra Kim,et al.  8Gb 3D DDR3 DRAM using through-silicon-via technology , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[33]  Arvind Kumar,et al.  Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..

[34]  Luca Benini,et al.  Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.

[35]  Joon-Sung Yang,et al.  Asymmetric ECC organization in 3D-memory via spare column utilization , 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[36]  Hajime Kobayashi,et al.  Alpha particle and neutron-induced soft error rates and scaling trends in SRAM , 2009, 2009 IEEE International Reliability Physics Symposium.

[37]  Tong Zhang,et al.  Architecture design exploration of three-dimensional (3D) integrated DRAM , 2009, 2009 10th International Symposium on Quality Electronic Design.